This research is on finding fundamental algorithms for synthesizing analog integrated circuit layouts from schematics. The algorithms use sensitivity-driven, graph-based methods. One set of algorithms uses the sensitivity of the circuit's performance to resistive and capacitive layout parasitics, thermal gradients, and fabrication process gradients to determine the relative positions of the circuit elements. Another set of algorithms generates the physical layout using the sensitivity data. These use a weighted constraint graphs approach that has been utilized in IC layout compaction. The graph weights and constraints are determined from the sensitivity data. An appropriate solution of the graph then yields the analog circuit layout. Layouts for analog circuits are still hand crafted by experts familiar with the circuit, system and manufacturing requirements. About 10% of application-specific designs, 50% of full custom designs and 80% of printed circuit board designs contain analog circuits. This research addresses a fundamental need in analog design: automation of the layout of circuit elements, and the P.I. is addressing important unsolved problems in this area. The novelty is in using a sensitivity analysis to determine relative placement of components on the chip. The principal investigator is a promising and competent young professor who should make significant contributions to the field.
