This research is on automation of the system level partitioning problem. In particular it addresses the task of partitioning a design so as to minimize the number of VLSI chips, while still satisfying constraints on system performance and chip parameters. The P.I. is generalizing a model for area estimation for standard cell chips to handle other layout design styles. This model plays a central role in developing system level partitioning tools by providing accurate estimates of the design layout areas. Complimentary tools which evaluate other aspects and merits of the design, such as power consumption, performance and pin count are being developed. The tools are being integrated into a spreadsheet-like design aid which will allow the designer to interact with the system. This research investigates system level partitioning of a design so as to optimize system design with respect to many parameters. The P.I. has novel ideas, which show promise in solving this complex problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.
