Testing sequential logic circuits and systems is the research subject. Solutions to this problem usually require costs that are, for many applications, too formidable to allow wide adoption. The goal is to find low cost techniques that reduce overhead of time, area and test data volume while maintaining high fault coverage. The approach is to use the notions of partial scan and partial BIST, which show promise in testing sequential circuits. One research thrust is to develop new measures of testability and a new criteria for scan element selection. A second is to systematically avoid elements of existing techniques that contribute to high costs. Effective test algorithms are being developed by using scan elements derived from information about the actual test generator. Substantial empirical evaluation with experimental tools using real circuits is being done.
