The proposed research investigates a logic network synthesis system, called SYLON, which is an extension and integration of the transduction method, negative gate synthesis algorithms, and previous synthesizers. Design tools in SYLON automatically solve various IC design problems. This research is on improving the system's capability to design compact networks with a large numbers of inputs. In addition, the system is being modified to design circuits which are fast on critical paths. Compaction of ROMs is being addressed using a novel technique of storing a disjunction of minterms at each crosspoint of memory lines, instead of a single minterm.
