Multiprocessor architectures are being widely investigated to overcome the performance limitations of traditional uniprocessor computer systems. VLSI and Wafer Scale Integration (WSI) of the entire multiprocessor architecture on a single wafer further enhance the system performance by eliminating long off-chip signal delay and interconnection. However, an efficient fault tolerance scheme is essential for the VLSI/WSI implementation to achieve a practical level of yield and reliability. This research is developing practical design methodologies capable of efficiently realizing large fault tolerant multiprocessor architectures of regular interconnection structure on a single large area VLSI circuit. The study is based on nonprobabilistic model to produce practical results which can be used in actual implementation. We are also developing efficient wafer testing and diagnosis schemes.
