Single-chip processor speeds are increaasing at a tremendous rate, providing raw processing power that is rapidly approaching that of mainframe computers. Unfortunately, external memory speeds are not exhibiting the same high rate of increase, and in high-performance single-chip processors external memory references are becoming a serious performance bottleneck. One way to reduce the impact of memory latency on performance is to incorporate architectural I/O queues between the processor and external memory. Analysis of a processor that employs such I/O queues (the PIPE processor) in its processor-memory interface indicates that these queues can and do provide significant performance improvements. However, the studies done so far have only looked at the effectiveness of I/O queues on scientific programs. The goal of this research is to more fully evaluate the overall effectiveness of I/O queues by generating a wide spectrum of benchmark programs and analyzing their execution on the PIPE simulator. These new benchmark programs will be produced by either creating a new optimizing compiler for the PIPE architecture that is capable of taking full advantage of the I/O queues, or by modifying the output of the compiler written for the ZS-1, a commercially available product that employs architectural queues similar to those used by the PIPE processor.
