An integrated approach towards the synthesis of high-bandwidth, low- latency interconnection networks is pursued that focuses on the interdependence of system architecture, VLSI characteristics and packaging technology. New designs of one-sided crosspoint switching modules that can provide several paths between communicating ports in multichip switches are being studied. An architecture solution is posed for the simultaneous switching noise problem and that has been traditionally tackled at the circuit design and packing levels. Novel schemes for fast arbitration and scheduling through the use of parallel bus-controllers are analyzed under a variety of message traffic conditions. An alternative approach uses artificial neural networks for contention resolution. Trade-offs between switch cost, performance and reliability are studies under these workloads for various chip sizes. Topological testing techniques are used for drastic reduction of test time. The research findings are being incorporated into a set of software tools recently developed at UT Austin for the computer-aided design of networks. Recent technological advances have prompted a resurgence of interest in cross bar-based designs in the industry, despite the requirement of O (N2) switches. Indeed, by considering current VLSI and packaging technology, it can be shown that power dissipation, current driving abilities and pinout limitations easily outweigh circuit density demands of switching networks. This research aims to lay the foundations for the cost-effective design of 128-1024 port crossbars with a sustained bandwidth of 1 GBytes per channel, that can form the core of the next generation of massively parallel machines and switching networks.
