The principal investigator continues his research on the design and evaluation of the memory hierarchy of high-performance systems. Uniprocessors as well as shared-memory multiprocessors will be studied. The studies will cover innovative architectural features, compiler support, and protocols and hardware synchronization primitives for several parallel programming models. In case of uniprocessors, a hardware-based preloading scheme that should reduce the number of misses in data caches, will be investigated. Compiler support for this hardware function will also be investigated. In the case of multiprocessors, various protocols and possibly enhanced synchronization primitives to cater to several consistency models will be investigated. The goal is to reduce the impact of the performance degradation components (large memory latency, processor stalling, network traffic) arising from the access to shared variables. Other topics include architectural features such as the use of the interconnection network, or one of its levels, as a component of the memory hierarchy. Trace-driven simulation will be the choice performance evaluation tool. Computer-intensive programs with large data sets drawn from scientific and CAD tool application will be instrumented.
