Bhattacharya This research is on: 1. hierarchical fault simulation in coarse-grain MIMD parallel computers or distributed systems; and 2. parallel test generation on MIMD parallel machines with and without shared memory. An investigation of two-dimensional circuit partitioning leading to two-dimensional, loosely-coupled, pipeline-like information flow in a distributed memory parallel computer, and partitioning of circuits employing partial scan design methodologies is being explored. Formal methods to analyze the computational complexity of the resultant parallel algorithms are being formulated. Implementations are being tested using industrial size benchmark circuits. A BDD-based approach is being taken for test generation. This has advantages in generating tests for large combinational circuits and sequential circuits. Algorithms are being explored for machines with shared memory, and for distributed-memory MIMD machines. Also being investigated are the generalization of BDD's to multi-valued decision diagrams, and the use of BDD-based test generation in a hierarchical design framework.
