The research is on chip-to-chip and on-chip interconnection problems. General formulations and efficient solutions to these problems are being explored. The focus is large chip/system designs with over a million transistors. Algorithms which minimize the interconnection delay and maximize circuit performance are being developed. Topics being addressed are: (1) timing driven global routing with bounded routing costs for both cell-based designs and building-block designs; (2) high-speed clock routing with minimum skew for cell-based and building-block designs; and (3) chip-to-chip interconnection problems for multichip packaging, including multilayer planer subset, multilayer via minimization, and transmission line problems.
