This research is on verification of circuit timing properties. The approach is to develop a multiple event timing verifier, which operates at gate level, represents multiple transitions on signals, and works on synchronous as well as asynchronous circuits. Algorithms that perform analysis in low order polynomial time and use a data representation that accurately captures the digital behavior of the system are being explored. Algorithm designs and related software being developed include functions such as: verifying circuits with non-trivial input timing, allowing multiple transitions on signals, doing functional analysis to eliminate false paths, allowing designers to input and examine data easily, verifying different clocking disciplines, and detecting various timing problems, such as clock rate not met, pulse shortening, hazards and races.
