The goal of this research is to develop cost-effective computer architectures that take advantage of rapidly changing technologies. The thrust of this work is in memory systems, which must supply information to increasingly-faster processors. As microprocessors approach the cycle time of supercomputers, the memory system (including I/O) becomes the main difference between a personal computer and a mainframe. Current research focuses on developing new techniques for analyzing memory system performance. One new approach uses a renewal-theoretic model to improve the accuracy of time-sampled trace-driven simulations. This model promises to substantially reduce simulation time (10-fold) with only a small decrease in accuracy (less that 10%). Another new technique is cache profiling. Similar to traditional execution time profilers, a cache profiler relates a program's cache performance to its source listing. Programmers and compiler writers can use this information to optimize the cache performance of their programs, restructuring code and changing algorithms. Computer architects use this tool to better understand cache access patterns, leading to improved cache designs, synchronization mechanisms, and prefetch strategies.
