While traditional video-rate applications have required no more than 10-bit resolution, new applications such as wide-dynamic- range imaging systems require at least 12-bit resolution. The requirements for such applications exceed the capabilities of present, state-of-the-art analog-to-digital converters using CMOS technologies. Progress in this area could dramatically reduce the cost of signal processing for these applications by allowing the use of digital signal processing techniques. The objectives of this project are: 1. to create techniques that can overcome the practical linearity limitations of analog-to-digital conversion interfaces without an associated loss in conversion rate and without the use of trimming or calibration, and, 2. to demonstrate these techniques by fabricating prototypes. The focus of 1. will be on pipelined, analog-to-digital conversion interfaces in CMOS technologies for high-resolution, video-rate applications. Circuit techniques that can overcome the practical linearity limitations will be studied. Since these techniques may reduce the maximum conversion rate, combinations of parallelism and digital-signal-processing techniques that have the potential to overcome such a reduction will be explored.
