The objective of this research is to build a high-level synthesis system which maps behavioral descriptions into register-transfer level designs with guaranteed performance. The approach is to examine subtasks of the high-level synthesis problem using theoretical tools necessary to understand the synthesis problem. Synthesis subtasks in the areas of scheduling and datapath allocation are being examined. Scheduling problems being investigated include: finding good heuristics to bound the search space so that good quality schedules for large size designs can be found in a timely way; use an integer programming formulation to solve the module selection problem; and develop a powerful, integer programming based, algorithm to optimally group functions into hardware modules. Register allocation problems include: devising a register allocation algorithm which will minimize both the number of registers and register transfers in the presence of loops and conditionals while accounting for interconnect cost; formulate the module allocation problem along the same lines as the register allocation; and investigate a good ordering of the allocation subtasks so that interconnects play a major role in the design process.
