Recent published results show that fractal geometry can be effectively used to model the skewness and degree of self- similarity exhibited by the memory-access patterns generated by processors. The fact that the fractal model can be used to predict the behavior of programs at many levels of the memory hierarchy, and that the performance of those levels can be in turn predicted, implies that memory access patterns are highly structured. Unfortunately, this structure is also highly irregular, and the vast majority of models that have been proposed to simulate program behavior must rely on over-simplifying and unrealistic assumptions of uniformity of access and/or of independence of access. Some preliminary results show that under some conditions, in particular when a process is allocated too little cache storage, its memory access pattern results in chaos in the cache, yielding poor cache performance. This research investigates the conditions under which chaos occurs, how cache design parameters influence it, how chaotic behavior influences cache performance, and applies these results to threading and cache partitioning, two methodologies that present potentially favorable conditions for chaos to appear.
