Pomeranz This research is on finding procedures to derive compact or small test sets that cover a comprehensive set of modeled faults, required to achieve high reliability of manufactured VLSI chips. A fault model that allows uniform representation of various fault models is being explored as the basis for generating small, yet comprehensive test sets. A set of tools to deal with different aspects of testing quality for combinational and fully scanned sequential circuits is being built. These are: 1. generation of small test sets for a comprehensive set of faults, including efficient treatment of path delay faults; 2. design for testability to allow faults undetectable in the original to be detected in a modified circuit; and 3. built in test pattern generation based on the test sets produced when stored pattern tests cannot be used.
