Liu The research is on algorithms for high level synthesis and layout of VLSI CAD designs. Algorithms for complex, large industrial type design problems are being developed. Research topics include: 1. high level synthesis with testability as an important goodness measure, 2. timing driven placement algorithms for EPGAs, and 3. channel and switchbox routing in which the effect of cross talk is to be taken into consideration. For the first problem, the effect of register allocation and functional unit binding on the testability of the circuit is being examined. Then the scheduling step is being examined. Research on the second problem is based on the notion of a "neighborhood graph" which is used in guiding an iterative improvement algorithm that produces placements which satisfy given timing constraints. An integer programming approach is being used for the third problem, because this avoids parallel long wires that are close together in the routing solution.
