Partitioning of large designs into smaller and more manageable parts is a very important design task. In high-level synthesis of register-transfer level designs, partitioning the specification is done prior to synthesizing the designs. If the input specification is control-dominated, the specification is partitioned into a set of states, or if the specification is data-dominated then it is partitioned into a set of graphs. In either case, the sets of the partition are synthesized independently and the complete design assembled together. This research re-examines the partitioning problem, outlines some concerns with existing techniques and presents a fresh approach to formulating and solving the partitioning problem. Specifically, the effort focuses on a data-path model which can be used for rapid-prototyping at the register-transfer level design and for partitioning of the input specification. The solution to these problems is achieved by scheduling the input specificiation onto the data-path model. The scheduling result can then be interpreted from a rapid-prototyping perspective or from a partitioning perspective as desired by the designer. This method will handle several new constraints such as communication and memory/register bank constraints, integrate floor planning with high-level design tools, and will accept a more complete input specification including loops and conditional branches. Our method will allow the designer to make tradeoffs which were hitherto not possible. An example is tradeoffs between communication overheads and performance of the design.
