Torrellas This research aims at improving the performance of memory hierarchies in scalable shared-memory multiprocessors. The research uses advanced performance monitoring hardware to characterize the performance of a real scalable machine, namely the 32-processor Cedar machine developed at the University of Illinois. Data from the characterization is being generalized to other machines, and optimizations such as new algorithms or hardware support are being evaluated. The research focuses on four research issues in memory hierarchies: 1. the performance of cache memories and prefetch buffers under frequent vector and block traffic; 2. the performance of Omega interconnection networks connecting the fastest layers of the memory hierarchy to global memory; 3. dynamic page migration and replication in the memory hierarchy to increase data locality; and 4. the cache memory performance of the operating system.
