Menon This research is on the development and implementation of optimization techniques for multilevel combinational logic circuits specified at the gate level. Logical implementation techniques which have been proven effective in test pattern generation are being used for this purpose. These techniques are being applied to three problems in logic optimization: area reduction, delay reduction, and testability enhancement. Relationships between signal values are being used to identify common subfunctions without generating expressions for them and putting them in any standard form. This approach is efficient and could substitute for Boolean factorization in logic optimization. Techniques for delay reduction involve replacing segments of long paths with shorter ones so that false paths are not created and undetectable faults are identified during delay reduction. The effectiveness of these techniques as supplements to an existing synthesis system are being investigated.
