This research investigated methodologies and efficient algorithms for performance-driven layout design and logic synthesis of high-speed, high-complexity VLSI systems. The research on performance-driven layout focuses on interconnect design process, including the development of accurate interconnect models which enable efficient layout optimization algorithms, efficient algorithms for circuit partitioning and clustering , interconnect-driven floorplan and placement, interconnect topology design with buffer insertin, simultaneous device and interconnect sizing, and clock layout optimization. The research on performance-driven logic synthesis mainly focus on synthesis and mapping for field-programmable gate-arrays (FPGAs), including optimal or near-optimal algorithms for structural and functional gate decomposition, minimum-delay technology mapping trade-off of delay and area in technology mapping, combined retiming, technology mapping, and resynthesis for clock period minimization, and automatic pipelining.
