9410457 Adve The objective of this research is to develop and evaluate techniques for reducing the impact of synchronization latency in shared-memory multiprocessors. Recent trends indicate that future microprocessors will employ aggressive techniques (e.g., multiple instruction issue, dynamic scheduling) to exploit instruction-level parallelism. Current shared-memory multiprocessors, however, usually require a processor to stall on synchronization reads until the read completes, precluding the full exploitation of future uniprocessors. The research studies two approaches for reducing the impact of synchronization latency: (a) overlapping latency of explicit synchronizations, and (b) using implicit synchronization (where possible) to eliminate synchronization latency. The key components of the study will be: (1) a practical hardware technique based on guarded instructions for overlapping acquire operations, (2) alleviating implementation overheads incurred with implicit synchronization by using a novel combination of explicit and implicit synchronization, (3) determining information in the form of high-level annotations that programmers can provide to enhance detection of instruction-level parallelism, and (4) a quantitative evaluation of the efficacy of the above techniques using extensive instruction-level simulations of real applications. This research is a necessary step towards enabling wider acceptance of parallel machines because it will enable machines to be more cost-effective by exploiting more fully the potential of next-generation microprocessors, and will broaden the supported class of applications by allowing the efficient execution of finer-grained applications. ***
