This research is on techniques and tools for automated logic design of low-power, semi-custom circuits. Digital circuits are specified as models in hardware description languages that can be readily compiled into finite-state machines. The latter are described by transition diagrams or by synchronous logic networks. These models are then used to solve logic synthesis problems in encoding sequential circuits, restructuring logic networks, and library binding. Tools for a comprehensive EDA system for low-power design are being developed.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
9421129
Program Officer
Robert B Grafton
Project Start
Project End
Budget Start
1995-04-15
Budget End
1999-09-30
Support Year
Fiscal Year
1994
Total Cost
$210,378
Indirect Cost
Name
Stanford University
Department
Type
DUNS #
City
Palo Alto
State
CA
Country
United States
Zip Code
94304