This research is on techniques for analysis of VLSI interconnect nets. Methods for predicting capacitance effects in VLSI circuitry, especially at rounded corners, are being investigated using asymptotic expansions. Secondly, methods to determine the voltage-current regime of nonlinear networks on a chip are being assessed. The approach is to model each interconnection network as a cascade of three terminal networks connected together at their ends. Each cascade can be described mathematically by a nonlinear operator. Computationally efficient analysis techniques are being developed.
