This research is on path delay testing. Tools and techniques to enable the development and evaluation of practical at-speed delay tests are being investigated. Test generators, fault simulators, and techniques for the design of design-for-testability (DFT) and built-in self-test (BIST) circuitry are being developed. Special attention is being paid to robust delay testing of the most critical circuit paths. Software tools which provide a practical testing solution for large circuits are being developed.
