To achieve maximum benefit from tiling, compiler optimization must exercise more control over data movement and storage assignments than is commonly done. Hierarchical tiling takes responsibility for several phases of compilation and code improvements that are traditionally done separately, such as scalar replacement, register allocation, generating message passing calls, and storage mapping. It uses the mechanisms of explicitly naming and copying data to control the movement of data up and down the memory hierarchy and to exploit all levels of parallelism. Its effectiveness as a systematic framework for hand-crafting highly optimized code has been tested on scientific applications for IBM SP1 system. This project will extend the research in compiler optimizations by investigating the following: (1) Develop a parameterized machine model that captures the architectural information needed to guide hierarchical tiling. (2) Study interactions between tiling at various levels of granularity. (3) Incorporate hierarchical tiling into the SUIF toolset. (4) Extend the work to disk storage, explicit I/O and implicit paging virtual memories. (5) Validate the approach using various programs on different parallel machines.
