This is an investigation into the application of asynchronous circuit design tools to a large, realistic example. The project is being carried out in conjunction with the Avalanche parallel architecture project at the University of Utah. The Cache and Communication Control Unit (CCCU) of the Avalanche multiprocessor, which is designed as a synchronous system, is being implemented as a self-timed system using the original specification for the Avalanche CCCU. To do this, problems in self-timed circuit design are being deeply investigated, with a particular focus on automating the design of high-performance self-timed systems. Chips embodying the designs are being fabricated through MOSIS, tested and evaluated.
