A methodology is to be developed which allows designers to do reliability prediction and reliability budgeting using a high-level functional description of the design. Prediction models at the gate and function level will be developed and verified using observed data. Under reliability budgeting a specified failure rate, or mean-time-to-failure, for the whole chip may be partitioned to provide reliability targets for smaller pieces and thus lower levels of abstraction. The work leads to the development of a new course in "Reliability Engineering for Integrated Circuits", which will provide a software environment where ICs may be subjected to stress test experiments in virtual environment at various design stages using observational data.
