The research objective is to develop methodologies for the design of giga-scale CMOS systems. A focus is high bit rate digital communications. The approach transcends boundaries between algorithmic, architectural, logic, circuit and technological aspects of the VLSI design methodology. The research has two parts. The first is an investigation of fundamental limits on power area speed and reliability in giga-scale computation. Activities include: (a) establishing non-empirical and achievable bounds on the power dissipation, area, speed and reliability for any given algorithm and implementation technology' and (b) exploring methods to achieve these fundamental bounds. In the second part, algorithms, architectures, and systems for design of high-bit rate communications systems are being investigated. Activities include: (a) developing power, area, and speed-optimal VLSI algorithms and architectures for high-bit rate digital communications and signal processing applications; and (b) building communications and signal processing applications; and (b) building practical systems for 155.52 Mb/s transmission over twisted-pair wiring for ATM and IMTV, and wireless spread-spectrum systems.
