The project investigates issues in memory hierarchy design and proposes solutions to bridge the increasing performance gap between the processor and memory. By observing the unequal time needed to perform cache tag access/comparison and to access cache data, this path imbalance can be exploited to achieve a more performance optimal cache design. The basic idea is to use an additional tag array record the status and location of the recently used lines in the cache data array. By recording the cache line locations in this subset of the tag array, the data access is decoupled from the tag access/comparison path for a shorter overall cache access time. In a multiprocessor system, cache coherence activities incur extra traffic to the heavily-loaded snooping bus and impose additional latency in accessing the data. By observing that references to the same memory location are often ordered at the software level, frequently rendering cache coherence activities are unnecessary and can be deferred until at the proper synchronization point. The infrastructure required, including a multiprocessor tracing facility, multiple-issue out-of-order execution processor models, and various memory hierarchy models, will be developed in this project. These tools will be enhanced with graphical user interfaces and used for instructional purposes to provide students with hands-on experience in evaluating difference architectural design tradeoffs.
