This project establishes an active research effort in microelectronic systems architecture that enhances the undergraduate curriculum in Computer Engineering, Computer Science and Electrical Engineering, and introduces students to new computer architectures, new technology and microelectronic systems. The ideas developed will be incorporated into the microprocessor and computer architecture curriculum along with new cooperative learning techniques. The focus of the research component is to devise and test Instruction Level Parallelism (ILP) techniques and mechanisms. Programmable Logic Devises, such as FPGAs, are used to implement rapid system prototyping of custom computer designs and are also used to implement custom components in reconfigurable architectures. Engineers and computer Science students are taught with highly participatory "active learning" methods such as cooperative learning which stimulate student interest and learning. By introducing students to teamwork in the engineering classroom, learning is enhanced, fruitful networking relationships are developed and students are able to adapt easily into other team environments. The rapid- prototyping platform developed for this effort is used for several upper division computer architecture and microprocessor courses and the cooperative learning pedagogy serves a national model.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Type
Standard Grant (Standard)
Application #
9624967
Program Officer
Robert B Grafton
Project Start
Project End
Budget Start
1996-06-15
Budget End
1999-06-30
Support Year
Fiscal Year
1996
Total Cost
$200,000
Indirect Cost
Name
California Polytechnic State University Foundation
Department
Type
DUNS #
City
San Luis Obispo
State
CA
Country
United States
Zip Code
93407