This is developing a methodology and efficient techniques for evaluating and/or predicting power dissipation of CMOS circuits. The major components of the proposed methodology are survey sampling techniques, automata-based sequence compaction techniques, a behavioral/logic level co-simulation engine, regression-based power macro-modeling techliques, and information-theoretic models of power dissipation. Special emphasis is being given to parasitic capacitance estimation, input data modeling, impact of memory hierarchy and circuit architecture, and effects of nonlinear delay equations and custom wire load models on accuracy/efficiency trade-offs of the estimators. Concurrently, CAD methodologies and techniques for minimizing the power dissipation in VLSI circuits and systems are being developed. These are: low power optimization techniques and prototype software programs for system-level partitioning and hardware/software codesign, communication synthesis, multiple supply voltage scheduling, activity-driven register allocation and binding, bus encoding, state assignment for interacting finite state machines, logic restructuring and simplification, timing-driven placement, routing and zero-skew clock tree construction. Finally, power management techniques such as (serial or parallel) gated clocks, stoppable clocks, and dynamic switching between power modes are being studied and automated.
