The goal of this research is to investigate extensions of a design methodology for a class of low noise integrated oscillators in the applications areas of telecommunications, high speed microprocessors, and oversampled data conversion. The goal of the teaching plan associated with this research is for the Analog Microelectronics Laboratory to become an integral resource for educating both undergraduates and graduate students in the complete integrated circuit design process. This project will improve the design of analog and mixed signal integrated circuits for telecommunication systems in which system-level performance is ultimately limited by fundamental circuit-level considerations. A critical component in any integrated communication system is an oscillatory that provides a time/frequency reference for the data transmission and detection process. The broad class of ring oscillators offer many advantages for integrated oscillator design, but until recently there were no procedures available to design for a desired level of noise performance. This project is based on a new design methodology for ring oscillators that has been proven successful to the frequencies up to 155 MHz in a bipolar IC process. The goal is to extend and broaden the low jitter oscillator design techniques to higher speed in the GHz range, reduced supply voltage of 3.3V and below, and other fabrication technologies including CMOS.
