In order to shorten product development cycles for integrated circuits and systems, pre-designed cores are widely used as part of the on-chip logic. Testing core-based designs is a major issue because the internal design of the core may not be known if it is intellectual property. In that case standard manufacturing test strategies will not suffice. This research is exploring new methodologies for testing chips with embedded cores. The approach is to find methods for synthesizing the user-defined logic, in which cores reside, so that the whole design meets area, performance and test criteria. Synthesis algorithms are being developed which address the following concerns: 1. Application of test vectors to inputs of the core. 2. Observation of outputs from the user-defined logic that drive the inputs of the core. 3. Testing the user-defined logic driven by the outputs of the core. 4. Observation of outputs from the core.
