In recent years CPU execution speed has increased at a much greater rate than DRAM access speed. This disparity has produced a large speed penalty for access to memory by today's computer systems, which may reach several hundred instructions within a few years. Performance of future computer systems may be limited by this effect to the speed of memory rather than the speed of logic. This project investigates a new memory architecture which reduces the speed gap. By integrating a small, wide cache on each DRAM IC, expected DRAM access time will be reduced. By employing dedicated high-performance connections between processor and memory, memory-bus latency will be eliminated. Finally, by incorporating hardware to predict memory access and prefetch data, DRAM latency will be further hidden. These innovations will be evaluated using architectural-level simulations based on traces of memory-intensive programs.
