This proposal deals with the automated layout of mixed analog and digital circuits. Optical interconnect interfaces which contain optoelectronic arrays integrated with digital processing capability require layouts in which noise sensitive analog circuits must be distributed throughout digital designs on a regular pitch for alignment with guided or free-space optical inputs. New layout tools must automatically incorporate application specific geometric constraints and analog noise requirements to produce layouts for these emerging technologies. The floor planning tool must have inputs from (1) a mask encapsulating the optical interface positioning requirements, called a keyhole mask,(2) standard cell and block compilers, and (3) the analog interfaces themselves. Problems being investigated are (1) creating a keyhole mask(2) modifying the Berkeley floor planning tool to provide feedback to the standard cell and block compilers based on keyhole mask inputs, and(3) modifying the Berkeley standard cell compiler to provide modified compilations based on inputs from the floor planning tool.
