*** 9734023 Tyson This project explores the interaction between code transformation performed during compilation and instruction set design. Several modifications in instruction set design are under investigation, each of which attempts to improve overall processor performance by increasing the amount of compile time information transmitted to the hardware at runtime. Some modifications, such as probabilistic prefetch or branch table indexing, amount to hints that may improve performance without requiring all implementations of an architecture to use the information. Others, such as imposition of FIFO semantics on one or more register identifiers, enable compilers to schedule resources and require that all implementations comply with the scheduling. Each of the modifications will be explored using both classroom projects for graduate courses and individual research by graduate students. Simulation and other tools arising from this project will be introduced into the undergraduate curriculum. ***
