The objective of this program is to design an efficient VLSI implementation for certain algebraic geometry codes, to fabricate a chip, and to identify applications where these codes would be competitive. The codes to be considered are Hermitian codes and other codes similar in structure. The advantage of these codes is that, for a given symbol size, they are longer than Reed- Solomon codes and can therefore take better advantage of the law of large numbers to give much greater error correction capability. A number of decoding algorithms for these codes exist, including those developed by the co-PIs. We will combine the best elements of these algorithms into an explicit computational algorithm that is well suited to VLSI implementation. The goal is to produce a chip that uses parallel processing, regular and simple structures, simple logic, and a minimal number of iterations. We will verify the logic design using a VHDL simulation. We will also identify systems where these codes would be appropriate and test the performance of the decoder in channel simulations appropriate to those applications.
