The goal of this research is to develop algoithms and tools for modeling hardware and software using a high-level programming language, or an HDL, and use it to develop algorithms for language-level "presynthesis" optimizations. Research activities being carried out under this grant include: (a) indentify semantic support for modeling reactive and structural components in a high-level language that preserves synthesizability of the resulting description; (b) explore the nature of the Don't Care (DC) information an design assertions that are used to optimize an HDL description; develop appropriate models to capture the DC information; (c) develop a tabular model of system behavior called. Timed Decision Tables (TDTs); (d) use TDT model transformations to restructure and rewrite HDL code for improved synthesis results. The research results are being used to develop a framework for language-level exploration and optimization of design alternatives for microelectronic systems.
