This research is exploring Complexity-Adaptive Processors (CAPs), a new microarchitecture within which hardware complexity, latency, and clock speed tradeoffs can be made on-the-fly at runtime. CAPs employ dynamic hardware structures for the major hardware functions of the processor and memory hierarchy. The organization and delay of these structures, as well as the clock speed of the chip, can be modified by the compiler, runtime system, or on-chip hardware to match application characteristics. This project is investigating CAP design options in order to assess the performance potential of this approach. Specific tasks being carried out include: (1) Investigating the dynamic hardware requirements of a variety of applications; (2) Evaluating the timing aspects of CAP hardware structures, including the tradeoff between varying latency and clock speed; (3) Devising configuration scheduling strategies for matching the hardware to the application; (4) Evaluating dynamic clocking alternatives; (5) Using simulation coupled with timing analysis to quantify the performance potential of the CAPs approach.
