Logic emulation systems provide an essential tool for the design of complex circuits, but there are significant obstacles to design of the mapping software that translates designs to the emulator. Such obstacles limit the potential to use logic emulation to simulate designs. This research is exploring new algorithms, distributed computing techniques, and quality/performance tradeoffs needed to increase the performance of the mapping software. The project is also developing a publicly available mapping flow to aid research into these systems, as well as set of large, realistic benchmark circuits. Finally, methods for integrating these devices into logic design curricula, allowing for near-speed execution of student designs, and much more realistic design experiences are being pursued.
