This project is a new approach to system-on-a-chip design, called deconstruction. The approach starts with an existing prefabricated, parameterized, reference design in silicon, composed of hundreds of Intellectual Property (IP) blocks, and then deconstructs it into the desired system by setting parameters. In contrast, the current approach is to construct a desired system by combining IP and then generating silicon. This approach has serious verification limitations. The techniques being developed focus on making deconstructed systems competitive with constructed systems in terms of design metrics like power, performance and size. The emphasis is on two issues relating to flexibility in reference designs: (1) Formalizing the notion of parameterized reference designs, consisting of a sound parameter classification scheme, and a precise method of specifying such parameters, and (2) Developing models and algorithms for parameter optimization, requiring system-level models of power and performance metrics from which metric values can be rapidly computed. Such optimization is being achieved by developing techniques based on cost ranges, rather than single cost values, to evaluate candidate solutions.
