On-chip inductance becomes an important design issue at transistor geometries of 0.25 mm and below. The primary goal of this project is to generate computer aided design tools and on-chip measurement techniques that will enable IC designers to cope with inductance related issues without the need for highly specialized knowledge or experimentation. The project has three thrusts. In thrust one, modeling and model reduction techniques will be developed that enable complex on-chip structures to be modeled and reduced so that they will be tractable for simulation. The techniques are based on rule-based extensions to PEEC and wavelet-based extraction. Thrust two is concerned with establishing an automated methodology to generate layout and performance margin guidance for use by designers. At the center of this effort is the identification of a set of generalized parameterized interconnect topologies that capture most of the important issues related to inductance control. Thrust three is concerned with measurement verification of the results of the other two thrusts and the determination of new automated in-situ measurement techniques.