On-chip inductance becomes an important design issue at transistor geometries of 0.25 mm and below. The primary goal of this project is to generate computer aided design tools and on-chip measurement techniques that will enable IC designers to cope with inductance related issues without the need for highly specialized knowledge or experimentation. The project has three thrusts. In thrust one, modeling and model reduction techniques will be developed that enable complex on-chip structures to be modeled and reduced so that they will be tractable for simulation. The techniques are based on rule-based extensions to PEEC and wavelet-based extraction. Thrust two is concerned with establishing an automated methodology to generate layout and performance margin guidance for use by designers. At the center of this effort is the identification of a set of generalized parameterized interconnect topologies that capture most of the important issues related to inductance control. Thrust three is concerned with measurement verification of the results of the other two thrusts and the determination of new automated in-situ measurement techniques.

Agency
National Science Foundation (NSF)
Institute
Division of Computer and Communication Foundations (CCF)
Application #
9988334
Program Officer
Sankar Basu
Project Start
Project End
Budget Start
2000-08-01
Budget End
2005-07-31
Support Year
Fiscal Year
1999
Total Cost
$420,000
Indirect Cost
Name
North Carolina State University Raleigh
Department
Type
DUNS #
City
Raleigh
State
NC
Country
United States
Zip Code
27695