The major thrust of this research is to develop a process for fabricating metal oxide semiconductor transistors on a silicon-germanium alloy epitaxial strained-layer, since such transistors are significantly faster than comparable silicon devices. The knowledge and understanding of silicon- germanium/silicon and silicon dioxide/silicon-germanium interfacial properties are crucial to the metal oxide semiconductor field effect transistor fabrication. First, silicon-germanium strained epitaxial layer will be grown on silicon using chemical vapor deposition process. The thermal oxide with thicknesses ranging from 250 to 500 Angstroms will be grown in a dry oxygen ambient. At this stage a few sample wafers will be subjected to high resolution transmission electron microscopy analysis to determine the misfit dislocation density at the silicon-germanium/silicon interface and the planarity of silicon dioxide/silicon-germanium interface. Metal oxide semiconductor capacitor structures will be fabricated on the remaining wafers and after metallization, quasi-static capacitance-voltage measurements will be taken to extract fixed charge density and interface trap charges. This work should lay the foundation to the manufacturability of metal oxide semiconductor field effect transistors on silicon- germanium/silicon alloys.
