Embedded systems with temporal constraints rely on timely scheduling and a priori knowledge of worst-case execution times. Static timing analysis derives safe bounds of WCETs but its applicability has been limited to hard real-time systems and small code snippets.
This research addresses these limitations of timing analysis for embedded systems. It contributes a novel approach to program analysis through parametric techniques of static timing analysis and provides innovative methods for exploiting them. The proposed techniques express worst-case execution time as a formula with the following benefits. First, static timing analysis becomes applicable to a wide class of embedded systems with variable loop bounds. Second, the benefits of parametric timing analysis provide new opportunities for dynamic and flexible scheduling decisions. Third, timing abstractions through the parametric approach enable the analysis of much larger programs than in the past. Finally, the techniques of static timing analysis, currently constrained to hard real-time system, become applicable to a much wider range of embedded systems with soft timing constraints. The broader impact is to increasingly expose students to embedded systems and to provide essential temporal assurances, which are a prerequisite for applying the results of hard and soft real-time scheduling for reliable embedded systems of national and economic importance.
