A five billion dollar industry has arisen over the last 25 years to develop and support tools and languages for synthesis, verification, and analysis of integrated circuits (ICs). Within the next five years, IC design will further change as it will be possible to provide enough transistors on a single chip for on the order of a hundred 16-bit processors. The systems will be designed to meet their performance goals through the exploitation of task level parallelism. These software-intensive systems will require modeling capabilities far beyond traditional computer-aided design tools. While software engineering techniques also contribute as design aids, they do not address the important aspect of performance; a key goal in the design of real, constrained systems. Central to the performance of these systems is the scheduling of the concurrent tasks onto concurrent processing elements.
Bottlenecks at one point in the system can cause system-wide performance degradations. This research will investigate defining a new level of modeling for the design of single-chip heterogeneous multiprocessing systems. The project will investigate the development of the underlying models that include processing resources, application tasks, and schedulers , and will develop a diagnostic aid based on the concurrent system model, and a simulator to be made available on a website. This research will define, demonstrate, and teach a new level of computer system modeling.
