On-board embedded systems, such as those found in avionics and flight control, shipboard computing, space shuttles, intelligent transport systems and instrumentations in medical and emergency facilities and vehicles, face greatly increased computational requirements both in terms of computation load as well as stringent constraints on timing guarantees. Two important issues that concern designers are efficient task scheduling to meet real-time constraints and the reduction of system-wide energy consumption for increased reliability.
Over 50% of failures in embedded systems are closely related to operating temperatures. These in turn are determined by the power consumption of the computational components of the system. This research seeks to develop peak power constrained scheduling methods to alleviate these reliability concerns. The project pursues the development of a peak power model to accurately describe the power constraints in a distributed embedded system, thereby allowing for a safe and effective use of the available computational resources during periods of high load. The uniqueness of this approach is its focus on distributed embedded systems with varying workloads. Power aware partitioning (PAP) schemes for hybrid architectures comprising processors and reconfigurable components, such as a Field Programmable Gate Arrays (FPGA), provide system designers with tuning capabilities for performance and real-time scheduling of system tasks. The project investigates the development of fast power-aware task partitioning algorithms in hybrid embedded systems.
