Due to the limits of power dissipation, the trend today in chip microarchitecture is to implement a multiprocessor with simple cores (Chip MultiProcessors or CMP) in which each core may run multiple threads concurrently (Chip MultiThreading or CMT). Future performance improvements will mostly come from supporting more and more threads in every microprocessor generation. In this context, there is renewed interest in designing highly scalable multithreaded algorithms. The goal of this project is to develop, evaluate and expand a generic model for parallel algorithms called STAMP (Synchronous, Transactional and Asynchronous MultiProcessing model). The STAMP model includes performance and power and is a compromise between simplicity, generality and good predictive value. The work in this project proceeds in two directions: design and exploration of parallel algorithm models, and application of the model to specific algorithms and applications. A simulation infrastructure for CMPs based on Simics called SimWattchMP is used for measuring performance and power and simulating system activity. If the model gains widespread acceptance, it will become a major abstracted platform on which designers and programmers of parallel algorithms can reliably design, program and evaluate their algorithms without the detailed knowledge of the machine and system. This will be critical to the evolution of hardware and software systems in the next 15 years. Research results will be widely disseminated by publications and will also be made available to the community at large through a project web page.
