This project, designing, implementing, and simulating architectural components to calculate their power requirements and developing detailed models of fault-tolerance, aims at acquiring appropriate infrastructure for the tasks (high-performance Blades, hard drive, Gigabit Ethernet, software). Proposing a shift in the design of embedded systems and microarchitectures, the work focuses on designing embedded systems that exploit application tolerance to reduced accuracy. Tolerance is often used to accommodate variations in quality of service in communication and network performance. While proposing a set of static and dynamic mechanisms to track computations involving control, the project pushes this tolerance into microarchitecture of embedded processors. The project examines two types of errors that benefit from tracking the data categories by evaluating the potential of mapping computations and data to
-Architectural components with differing levels of soft error protection and -Reduced precision components, that save power through voltage overscaling and/or power gating. Proposed are a general compiler and architecture mechanisms that will function on any code, but are designed to exploit applications that can trade some form of output fidelity for relaxed accuracy requirements.
