The research tasks of this project aim at building a sound knowledge base and systematic design framework for dependable and predictable integration of next generation COTS-based embedded systems. In modern computer architectures, peripherals autonomously can initiate data transfers and contend for bus transactions. Most of the real-time systems literature is focused mainly on how to properly partition CPU cycles paying less attention to the co-scheduling problem of the CPU and I/O ``smart'' peripherals. Unfortunately, temporal isolation guaranteed at the CPU level can be globally violated whenever the CPU tries to access the shared bus which is currently locked by another master device. To guarantee the dependable and predictable behavior of next generation embedded systems, the following research tasks are pursued:
1) The research introduces the novel idea of a ``hardware server,'' implemented on a customized smart bridge. In the architecture being developed, a smart bridge separates a group of peripherals from the rest of the system shielding the system itself from undesirable behaviors of peripherals. The smart bridge is implemented using a FPGA-based full system-on-chip (SoC).
2) Relevant bus transactions from untrusted components are montiored since it can be very hard or impossible to be shown that commercial off-the-shelf (COTS) devices satisfy system assumptions. The rationale is to optimistically assume that all assumptions hold and then to monitor the runtime behavior of COTS components against their assumed specifications. If violations are detected, then an appropriate recovery measure is taken. Monitoring is decentralized: events are filtered and communicated to FPGA-based monitors by corresponding smart bridges. In addition, specifications are synthesized into low-level monitors via translations to intermediate timed automata.
